Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
A Highly-Efficient Technique for Reducing Soft Errors in Static CMOS Circuits
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger
Journal of Electronic Testing: Theory and Applications
Construction of SEU tolerant flip-flops allowing enhanced scan delay fault testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Soft errors are functional failures resulting from the latching of single-event transients (transient voltage fluctuations at a logic node or SETs) caused by high-energy particle strikes or electrical noise. Due to technology scaling and reduced supply voltages, they are expected to increase by several orders of magnitude in logic circuits. Both combinational and sequential logic circuits are expected to be affected. Many different latch designs to prevent soft errors due to particle strikes on the latch nodes have been proposed. We review these designs and compare them based on their robustness and their power and performance overheads. We also propose new latch designs, the best of which is vulnerable only to a single-event, multiple-upset without any delay overhead and consumes only 40% power of a standard latch. We expect this work will help designers to select latches for applications where soft error is an important design metric.