A Low Power Soft Error Suppression Technique for Dynamic Logic

Authors:
Jeetendra Kumar;Mehdi B. Tahoori
Affiliations:
Analog Devices Inc.;Northeastern University
Venue:
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Year:
2005

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Abstract

As the device sizes are shrinking, the next generation combinational logic will also become equally susceptible to soft errors as the memory elements. In this paper, we propose a novel technique to minimize the impact of soft errors in domino logic by using complementary pass transistor devices and additional weak keeper to selectively isolate the logic gates struck by single event upsets (SEUs). Experimental analysis shows that this technique achieves soft error suppression with no extra power consumption and modest area (2.6%) and delay (13.6%) overhead.