On Transistor Level Gate Sizing for Increased Robustness to Transient Faults

Authors:
J. M. Cazeaux;D. Rossi;M. Omana;C. Metra;A. Chatterjee
Affiliations:
University of Bologna;University of Bologna;University of Bologna;University of Bologna;Georgia Institute of Technology
Venue:
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Year:
2005

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Abstract

In this paper we present a detailed analysis on how the critical charge (Q_crit) of a circuit node, usually employed to evaluate the probability of transient fault (TF) occurrence as a consequence of a particle hit, depends on transistorsý sizing. We derive an analytical model allowing us to calculate a nodeýs Q_crit given the size of the nodeýs driving gate and fan-out gate(s), thus avoiding time costly electrical level simulations. We verified that such a model features an accuracy of the 97% with respect to electrical level simulations performed by HSPICE. Our proposed model shows that Q_crit depends much more on the strength (conductance) of the gate driving the node, than on the node total capacitance. We also evaluated the impact of increasing the conductance of the driving gate on TFsý propagation, hence on Soft Error Susceptibility (SES).We found that such a conductance increase not only improves the TF robustness of the hardened node, but also that of the whole circuit.