On Transistor Level Gate Sizing for Increased Robustness to Transient Faults
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
Latch Susceptibility to Transient Faults and New Hardening Approach
IEEE Transactions on Computers
Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Soft-Error Hardening Designs of Nanoscale CMOS Latches
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
New configuration memory cells for FPGA in nano-scaled CMOS technology
Microelectronics Journal
Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications
Microelectronics Journal
Low-leakage soft error tolerant port-less configuration memory cells for FPGAs
Integration, the VLSI Journal
Journal of Electronic Testing: Theory and Applications
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This paper proposes a new hardening design for an 11 transistors (11T) CMOS memory cell at 32 nm feature size. The proposed hardened memory cell overcomes the problems associated with the previous design by utilizing novel access and refreshing mechanisms. Simulation shows that the data stored in the proposed hardened memory cell does not change even for a transient pulse of more than twice the charge than a conventional memory cell. Moreover it achieves 55% reduction in power delay product compared to the DICE cell (with 12 transistors) providing a significant improvement in soft error tolerance. Simulation results are provided using the predictive technology file for 32 nm feature size in CMOS.