A 11-transistor nanoscale CMOS memory cell for hardening to soft errors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
New configuration memory cells for FPGA in nano-scaled CMOS technology
Microelectronics Journal
SEU tolerant robust latch design
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications
Microelectronics Journal
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CMOS nanometric technologies are increasingly sensitive to soft errors, including SEUs affecting storage cells and SETs initiated in the combinational logic, and eventually captured by some latches or flip-flops. SEUs affecting latches or flip-flops are by far the largest soft error rate (SER) contributor in logic. Thus, developing cost-efficient hardened storage cells to cope with SEUs in latches and flip-flops (but also in some memories difficult to protect by ECC ) is of increasing importance. This paper proposes a new principle for designing low-cost highly robust storage cells and several transistor level implementations.