Latch Design for Transient Pulse Tolerance
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
A delay-efficient radiation-hard digital design approach using CWSP elements
Proceedings of the conference on Design, automation and test in Europe
Tunable Transient Filters for Soft Error Rate Reduction in Combinational Circuits
ETS '08 Proceedings of the 2008 13th European Test Symposium
A new family of sequential elements with built-in soft error tolerance for dual-VDD systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture Design for Soft Errors
Architecture Design for Soft Errors
DFT '09 Proceedings of the 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Construction of SEU tolerant flip-flops allowing enhanced scan delay fault testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fault secure encoder and decoder for nanomemory applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Circuit-level design approaches for radiation-hard digital electronics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Gate sizing to radiation harden combinational logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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With the scaling of technology node and voltage levels, VLSI circuits are facing the challenge of tolerance to soft errors normally caused by alpha particle or neutron hits. These radiation strikes, resulting into bit upsets referred to as single-event upsets (SEUs), may be catastrophic in few sensitive applications and severely undermine the quality and reliability in other applications. In this paper we propose two novel SEU tolerant latch designs RHL-A and RHL-B. Our latch designs are area efficient in comparison with the earlier proposals. Simulation results show that the proposed latch designs is extremely robust as it does not flip even for a transient pulse with 58 times the Qcrit of a standard latch cell. Compared to standard latch, RHL-A uses 40 percent more transistors and is 65 percent slower, whereas RHL-B uses 60 percent more transistors but is 65 percent faster.