Logic SER Reduction through Flipflop Redesign
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Soft error reduction in combinational logic using gate resizing and flipflop selection
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
SEU tolerant robust latch design
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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