Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion
Journal of Electronic Testing: Theory and Applications
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Analysis and optimization of fault-tolerant embedded systems with hardened processors
Proceedings of the Conference on Design, Automation and Test in Europe
SEU tolerant robust latch design
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design
Microelectronics Journal
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This paper describes a tunable transient filter (TTF) design for soft error rate reduction in combinational logic circuits. TTFs can be inserted into combinational circuits to suppress propagated single-event upsets (SEUs) before they can be captured in latches/flip-flops. TTFs are tuned by adjusting the maximum width of the propagated SEU that can be suppressed. TTFs require 6--14 transistors, making them an attractive cost-effective option to reduce the soft error rate in combinational circuits. A global optimization approach based on geometric programming that integrates TTF insertion with dual-VDD and gate sizing is described. Simulation results for the 70nm process technology indicate that a 17--48X reduction in the soft error rate can be achieved with this approach.