Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Transient Fault Sensitivity Analysis of Analog-to-Digital Converters (ADCs)
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Latch Susceptibility to Transient Faults and New Hardening Approach
IEEE Transactions on Computers
Propagation of Transients Along Sensitizable Paths
IOLTS '08 Proceedings of the 2008 14th IEEE International On-Line Testing Symposium
Tunable Transient Filters for Soft Error Rate Reduction in Combinational Circuits
ETS '08 Proceedings of the 2008 13th European Test Symposium
Reliable system design: models, metrics and design techniques
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A systematic approach to modeling and analysis of transient faults in logic circuits
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Soft-Error Hardening Designs of Nanoscale CMOS Latches
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Analysis and Design of Resilient VLSI Circuits: Mitigating Soft Errors and Process Variations
Analysis and Design of Resilient VLSI Circuits: Mitigating Soft Errors and Process Variations
High-Performance Robust Latches
IEEE Transactions on Computers
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Soft-error interference is a crucial design challenge in the advanced CMOS VLSI circuit designs. In this paper, we proposed a SEU Isolating DICE latch (Iso-DICE) design by combing the new proposed soft-error isolating technique and the inter-latching technique used in the DICE (Calin et al., 1996 [1]) design. To further enhance SEU-tolerance of DICE design, we keep the storage node pairs having the ability to recover the SEU fault occurring in each other pair but also avoid the storage node to be affected by each other. To mitigate the interference effect between dual storage node pairs, we use the isolation mechanism to resist high energy particle strikes instead of the original interlocking design method. Through isolating the output nodes and the internal circuit nodes, the Iso-DICE latch can possess more superior SEU-tolerance as compared with the DICE design (Calin et al., 1996 [1]). As compared with the FERST design (Fazeli, 2009 [2]) which performs with the same superior SEU-tolerance, the proposed Iso-DICE latch consumes 50% less power with only 45% of power delay product in TSMC 90nm CMOS technology. Under 22nm PTM model, the proposed Iso-DICE latch can also perform with 11% power delay product saving as compared with the FERST design (Fazeli, 2009 [2]) that performs with the same superior SEU-tolerance.