Transient Fault Sensitivity Analysis of Analog-to-Digital Converters (ADCs)

Authors:
Mandeep Singh;Ravinder Rachala;Israel Koren
Affiliations:
-;-;-
Venue:
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
Year:
2001

Citing 0
Cited 4

Fault Sensitivity and Tolerance of Successive Approximation and Δ-Σ Analog-to-Digital Converters (ADCs)

Analog Integrated Circuits and Signal Processing
Fault-sensitivity analysis and reliability enhancement of analog-to-digital converters

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design

Microelectronics Journal

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Abstract

Abstract: Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an ADC to convert the collected data to digital form and a digital unit to process it. It is important to analyze the fault sensitivities of each of these to effectively gauge and improve the reliability of the system. This paper addresses the issue of fault sensitivity of ADCs. A generic methodology for analyzing the fault sensitivity of ADCs is presented. A novel concept of "node weights" specific to a-particle induced transient faults is introduced to increase the accuracy of such an analysis.