IBM experiments in soft fails in computer electronics (1978–1994)
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Reliability Enhancement of Analog-to-Digital Converters (ADCs)
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Incorporating Fault Tolerance in Analog-to-Digital Converters (ADCs)
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Transient Fault Sensitivity Analysis of Analog-to-Digital Converters (ADCs)
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
Hi-index | 0.00 |
The reliability of ADCs used in highly critical systems can be increased by applying a two-step procedure starting with sensitivity analysis followed by redesign. The sensitivity analysis is used to identify the most sensitive blocks which could then be redesigned for better reliability by incorporating fault tolerance. This paper illustrates the steps involved in incorporating fault tolerance in an ADC. Two redesign techniques to improve the reliability of a circuit are presented. Novel selective node resizing algorithms for increased tolerance against α-particle induced transients are discussed.