SEU tolerant robust latch design
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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In this paper we propose a new robust latch, referred to as HiPeR latch. It is insensitive to TFs affecting its internal and output nodes by design (independently of the size of its transistors), thus being scalable with technology node. It presents better or comparable robustness to TFs compared to the most recent latches in literature, while providing better characteristics in terms of performance at comparable area and power cost.