Low-leakage asymmetric-cell SRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage in nano-scale technologies: mechanisms, impact and design considerations
Proceedings of the 41st annual Design Automation Conference
Soft error rate estimation and mitigation for SRAM-based FPGAs
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Improving soft-error tolerance of FPGA configuration bits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA
Proceedings of the conference on Design, automation and test in Europe
Latch Susceptibility to Transient Faults and New Hardening Approach
IEEE Transactions on Computers
Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
An Overview of Low-Power Techniques for Field-Programmable Gate Arrays
AHS '08 Proceedings of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems
Zero-Hardened SRAM Cells to Improve Soft Error Tolerance in FPGA
IITA '08 Proceedings of the 2008 Second International Symposium on Intelligent Information Technology Application - Volume 02
Mitigating soft errors in SRAM-based FPGAs by decoding configuration bits in switch boxes
Microelectronics Journal
A 11-transistor nanoscale CMOS memory cell for hardening to soft errors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
New configuration memory cells for FPGA in nano-scaled CMOS technology
Microelectronics Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Active leakage power optimization for FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications
Microelectronics Journal
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As technology scales the area constraint is becoming less restrictive, but soft error rate and leakage current are drastically increased with technology down scaling. Therefore, in nano-scaled CMOS technology, the reduction of soft error rate and leakage current is the most important challenge in designing field programmable gate arrays (FPGA). To overcome these difficulties, based on the observations that most configuration bit-streams of FPGA are zeros across different designs and that configuration memory cells are not directly involved with signal propagation delays in FPGA, this paper presents a new family of configuration memory cells for FPGAs in nano-scaled CMOS technology. When zeros are stored in the cells, the injected glitch due to particle strike is removed from the stroked node by pull-up or pull-down network of the cells. Thus, our proposed cells are completely hardened and cannot flip from particle strikes at the sensitive cell nodes when zeros are stored in the cells. Furthermore, in the proposed cells, when zeros are stored, the sub-threshold leakage current components are reduced by using stacks of transistors in series. These new cells are port-less and the storage nodes of cells are manipulated through the transistors which apply the supply voltages to the cell. Simulation results show that the proposed cells are working correctly during their configuration and idle cycles and that our cells have a lower soft error rate and leakage current in 22-nm, as well as 65-nm technologies.