Soft error-aware design optimization of low power and time-constrained embedded systems
Proceedings of the Conference on Design, Automation and Test in Europe
Impact of voltage scaling on nanoscale SRAM reliability
Proceedings of the Conference on Design, Automation and Test in Europe
New configuration memory cells for FPGA in nano-scaled CMOS technology
Microelectronics Journal
Low-power multiple-bit upset tolerant memory optimization
Proceedings of the International Conference on Computer-Aided Design
Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications
Microelectronics Journal
Impact of soft errors in a jet engine controller
SAFECOMP'12 Proceedings of the 31st international conference on Computer Safety, Reliability, and Security
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Virtualization for safety-critical, deeply-embedded devices
Proceedings of the 28th Annual ACM Symposium on Applied Computing
Evaluating the feasibility of using memory content similarity to improve system resilience
Proceedings of the 3rd International Workshop on Runtime and Operating Systems for Supercomputers
Low-leakage soft error tolerant port-less configuration memory cells for FPGAs
Integration, the VLSI Journal
Thermal analysis of periodic real-time systems with stochastic properties: an analytical approach
Proceedings of the 21st International conference on Real-Time Networks and Systems
Journal of Systems and Software
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With each technology node shrink, a silicon chip becomes more susceptible to soft errors. The susceptibility further increases as the voltage is scaled down to save energy. Based on analysis on cells from commercial libraries, we have quantified the increase in the soft error probability across 65nm and 45nm technology nodes at different supply voltages using the Qcrit based simulation methodology. The Qcrit for both bit cells and latches decreases by ~30% as the designs are scaled from 65nm to 45nm. This decrease is expected to continue with further technology scaling as well. The results show that at nominal voltage, the Qcrit for a latch is just ~20% more than that of the bit cell in sub-65nm technology nodes. Further, as the voltage is scaled from 1V to 0.4V, Qcrit decreases by ~5X which substantially increases the probability of an upset if a particle strike happens. This work shows that in sub-65nm technology nodes with aggressive voltage scaling, it is equally critical to solve the soft error problems in logic (latches, flip-flops) as it is in SRAMs.