IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Soft-error Monte Carlo modeling program, SEMM
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Critical charge calculations for a bipolar SRAM array
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
SEAT-LA: A Soft Error Analysis Tool for Combinational Logic
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
Efficient error detection codes for multiple-bit upset correction in SRAMs with BICS
ACM Transactions on Design Automation of Electronic Systems (TODAES)
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test
RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
Error-correcting codes for semiconductor memory applications: a state-of-the-art review
IBM Journal of Research and Development
A novel column-decoupled 8T cell for low-power differential and domino-based SRAM design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Soft-Error-Rate-Analysis (SERA) Methodology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we propose a framework for analyzing Soft Error Rates (SER) including Multiple-Bit Upsets (MBU). Then, using this framework, we optimize the soft error tolerant voltage (Vtol) and interleaving distance (ID) of low-power, error-tolerant memories. Experimental results show that the total power can be reduced by an average of 30.5% with Vtol optimization and an average of 40.9% by simultaneously considering Vtol and ID together when compared to worst-case design practices.