Modeling the cosmic-ray-induced soft-error rate in integrated circuits: an overview
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Single event transients in combinatorial circuits
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Proceedings of the 20th annual conference on Integrated circuits and systems design
Mitigating Soft Errors in SRAM Address Decoders Using Built-in Current Sensors
Journal of Electronic Testing: Theory and Applications
Design of self correcting radiation hardened digital circuits using decoupled ground bus
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Low-power multiple-bit upset tolerant memory optimization
Proceedings of the International Conference on Computer-Aided Design
A Bulk Built-In Voltage Sensor to Detect Physical Location of Single-Event Transients
Journal of Electronic Testing: Theory and Applications
Reliable on-chip systems in the nano-era: lessons learnt and future trends
Proceedings of the 50th Annual Design Automation Conference
A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic
Journal of Electronic Testing: Theory and Applications
An infrastructure for accurate characterization of single-event transients in digital circuits
Microprocessors & Microsystems
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Connecting a built-in current sensor in the design bulk of a digital system increases sensitivity for detecting transient upsets in combinational and sequential logic. SPICE simulations validate this approach and show only minor penalties in terms of area, performance, and power consumption.