IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Modeling the cosmic-ray-induced soft-error rate in integrated circuits: an overview
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Proposal of a timing model for CMOS logic gates driving a CRC &pgr; load
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Single event transients in dynamic logic
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Device and architecture concurrent optimization for FPGA transient soft error rate
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Mitigating Soft Errors in SRAM Address Decoders Using Built-in Current Sensors
Journal of Electronic Testing: Theory and Applications
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The single event upset (SEU) mechanism in MOS circuits is normally investigated by Spice-like circuit simulation. The problem is that electrical simulation is time consuming and must be performed for each different circuit topology, incident particle and track.This work presents an accurate and computer efficient analytical model for the evaluation of integrated circuit sensitivity to SEU. The key idea of this work is to exploit a model that allows the rapid determination of the sensitivity of any MOS circuit, without the need to run circuit simulations. To accomplish the task, but single event transient generation and its propagation through circuit logic stages is characterized and modeled.The model predicts whether or not a particle hit generates a transient pulse (bit flip) which may propagate to the next logic gate or memory element. The propagation of the transient pulse through each stage of logic until it reaches a memory element is also modeled. Both duration and amplitude of the transient pulse are attenuated as it propagates through the logic gates. A simple, first order model for the degradation of a transient pulse as it is propagated through a chain of logic gates is also proposed. The model considers the electrical masking properties of the logic gates through which the pulse propagates.Model derivation is in strong relation with circuit electrical behavior, being consistent with technology scaling. The model is suitable for integration into CAD-Tools, intending to make automated evaluation of MOS circuit sensitivity to SEU possible, as well as automated estimation of soft error rate.