Proposal of a timing model for CMOS logic gates driving a CRC &pgr; load

Authors:
Akio Hirata;Hidetoshi Onodera;Keikichi Tamaru
Affiliations:
Department of Communications and Computer Engineering, Kyoto University, Sakyo-ku, Kyoto, 606-8501, Japan;Department of Communications and Computer Engineering, Kyoto University, Sakyo-ku, Kyoto, 606-8501, Japan;Department of Communications and Computer Engineering, Kyoto University, Sakyo-ku, Kyoto, 606-8501, Japan
Venue:
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Year:
1998

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