Power estimation for a submicron CMOS inverter driving a CRC interconnect load

Authors:
Hung-Jung Chen;Bradley S. Carlson
Affiliations:
Department of Electrical and Computer Engineering, State University of New York at Stony Brook, Stony Brook, NY;Department of Electrical and Computer Engineering, State University of New York at Stony Brook, Stony Brook, NY
Venue:
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Year:
2000

Citing 3
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Abstract

We present an analytical expression for the evaluation of the short-circuit power dissipation in a CMOS inverter driving a CRC interconnect load. The validity of the model is much improved over previous works that inaccurately model a MOS transistor as a piecewise linear element, inadequately consider short-circuit current, or inappropriately apply the total capacitance approach. Moreover, our method requires less characterization effort while considering short-channel effects and secondary effects such as short-circuit current and coupling capacitance. As a result of this analysis, the results from proposed model are very close to those of SPICE3.