New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs

Authors:
Dan Alexandrescu;Lorena Anghel;Michael Nicolaidis
Affiliations:
-;-;-
Venue:
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Year:
2002

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Abstract

This work considers a SET (single event transient) fault simulation technique to evaluatethe probability that a transient pulse, born in the combinational logic, may be latched in astorage cell. Fault injection procedures and a fast fault simulation algorithm for transientfaults were implemented around an event driven simulator. A statistical analysis wasimplemented to organize data sampled from simulations. The benchmarks show that theproposed algorithm is capable of injecting and simulating a large number of transient faults incomplex designs. Also specific optimizations have been carried out, thus greatly reducing thesimulation time compared to a sequential fault simulation approach.