Modulo 3 Residue Checker: New Results on Performance and Cost
IEEE Transactions on Computers
Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
A TMR Scheme for SEU Mitigation in Scan Flip-Flops
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
A delay-efficient radiation-hard digital design approach using CWSP elements
Proceedings of the conference on Design, automation and test in Europe
Variation-tolerant hierarchical voltage monitoring circuit for soft error detection
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion
Journal of Electronic Testing: Theory and Applications
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With shrinking device sizes, modern digital circuits are becoming increasingly susceptible to transient errors due to charged particle strikes on the sensitive nodes of the circuit. In this paper we present a simple technique to implement self correcting, radiation hardened digital circuits through the use of a decoupled ground bus. The technique relies on using the error signal as a design variable in the logic being realized and employs a state machine based design approach for combinational logic design. Simulation results show that the proposed technique is reliable over all corners and robust against random process and mismatch variations. Our technique results in average 29.43% delay, 13.8% power and negligible area overhead than non hardened static and domino designs.