Error Coding for Arithmetic Processors
Error Coding for Arithmetic Processors
Reliability modeling techniques for self-repairing computer systems
ACM '69 Proceedings of the 1969 24th national conference
A 1.3GHz fifth generation SPARC64 microprocessor
Proceedings of the 40th annual Design Automation Conference
Design of self correcting radiation hardened digital circuits using decoupled ground bus
Proceedings of the 20th symposium on Great lakes symposium on VLSI
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The performance and cost of a modulo-3 residue code checker that has been attached to a pipelined serial multiplier to provide a concurrent self-test capability are considered. Analytical results are derived for error detection coverage and minimum error latency; these quantities are observed to be in agreement with simulation results obtained by using ISPS, a register-transfer language. The residue checker error detection coverage and minimum error latency are observed to be dependent on the statistical properties of the multiplier input operands. The checker and serial multiplier were implemented in 4- mu m NMOS, using a standard cell design. The residue code checker required approximately half of the total silicon area.