Cost reduction and evaluation of temporary faults detecting technique
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies
ETS '07 Proceedings of the 12th IEEE European Test Symposium
XOR-Based Low Cost Checkers for Combinational Logic
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
Transient Error Detection and Recovery in Processor Pipelines
DFT '09 Proceedings of the 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Differential fault analysis on AES key schedule and some countermeasures
ACISP'03 Proceedings of the 8th Australasian conference on Information security and privacy
Transient Fault and Soft Error On-die Monitoring Scheme
DFT '10 Proceedings of the 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems
DFT '11 Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
Timing issues for an efficient use of concurrent error detection codes
LATW '11 Proceedings of the 2011 12th Latin American Test Workshop
Hi-index | 0.00 |
This paper presents a new recovery scheme for dealing with short-to-long duration transient faults in combinational logic. The new scheme takes earlier into account results of concurrent error detection (CED) mechanisms, and then it is able to perform shorter recovery latencies than existing similar strategy. The proposed scheme also requires less memory resources to save input contexts of combinational logic blocks. In addition, this work also proposes a taxonomy of CED techniques. It allows pointing out which are the necessary recovery resources as well as identifying which are the types of CED mechanisms that can be used with the new recovery scheme of this paper. The effectiveness of the proposed scheme was evaluated through electrical-level simulations. For all short-to-long duration transient-fault injections, it was never slower than state-of-art similar strategy, and indeed its recovery latency was faster for 34 % of the simulated faulty scenarios.