A soft error analysis tool for high-speed digital designs
Proceedings of the 2nd international conference on Ubiquitous information management and communication
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 46th Annual Design Automation Conference
Accurate linear model for SET critical charge estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of asynchronous circuits for high soft error tolerance in deep submicrometer CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design as you see FIT: system-level soft error analysis of sequential circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Radiation-induced Soft Errors: A Chip-level Modeling Perspective
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power multiple-bit upset tolerant memory optimization
Proceedings of the International Conference on Computer-Aided Design
Inspection resistant memory: architectural support for security from physical examination
Proceedings of the 39th Annual International Symposium on Computer Architecture
Proceedings of the International Conference on Computer-Aided Design
CEP: Correlated Error Propagation for Hierarchical Soft Error Analysis
Journal of Electronic Testing: Theory and Applications
Formal performance analysis for faulty MIMO hardware
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low-cost, systematic methodology for soft error robustness of logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
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We present a soft-error-rate analysis (SERA) methodology for combinational and memory circuits. SERA is based on a modeling and analysis approach that employs a judicious mix of probability theory, circuit simulation, graph theory, and fault simulation. SERA achieves five orders of magnitude speedup over Monte Carlo-based simulation approaches with less than 5% error. Dependence of the soft-error rate (SER) of combinational logic circuits on a supply voltage, clock period, latching window, circuit topology, and input vector is explicitly captured and studied for a typical 0.18-mum CMOS process. Results show that the SER of logic is a much stronger function of timing parameters than the supply voltage. Also, an SER peaking phenomenon in multipliers is observed where the center bits have an SER that are orders of magnitude greater than those of the LSBs and the MSBs. An increase of up to 25% in the SER for multiplier circuits of various sizes has been observed as technology scales from 0.18 to 0.13 mum