Integration, the VLSI Journal
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Iterative ring and power-aware design techniques for self-timed digital circuits
Iterative ring and power-aware design techniques for self-timed digital circuits
Asynchronous Circuits Sensitivity to Fault Injection
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Asynchronous circuits transient faults sensitivity evaluation
Proceedings of the 42nd annual Design Automation Conference
Hardening Techniques against Transient Faults for Asynchronous Circuits
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Efficient Failure Detection in Pipelined Asynchronous Circuits
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Self-Healing Asynchronous Arrays
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
Soft Error Hardening for Asynchronous Circuits
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Error-correcting codes for semiconductor memory applications: a state-of-the-art review
IBM Journal of Research and Development
Analysis and optimization of nanometer CMOS circuits for soft-error tolerance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Soft-Error-Rate-Analysis (SERA) Methodology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Designing robust threshold gates against soft errors
Microelectronics Journal
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As the devices are scaling down, the combinational logic will become susceptible to soft errors. The conventional soft error tolerant methods for soft errors on combinational logic do not provide enough high soft error tolerant capability with reasonably small performance penalty. This paper investigates the feasibility of designing quasi-delay insensitive (QDI) asynchronous circuits for high soft error tolerance. We analyze the behavior of null convention logic (NCL) circuits in the presence of particle strikes, and propose an asynchronous pipeline for soft-error correction and a novel technique to improve the robustness of threshold gates, which are basic components in NCL, against particle strikes by using Schmitt trigger circuit and resizing the feedback transistor. Experimental results show that the proposed threshold gates do not generate soft errors under the strike of a particle within a certain energy range if a proper transistor size is applied. The penalties, such as delay and power consumption, are also presented