Asynchronous circuits transient faults sensitivity evaluation
Proceedings of the 42nd annual Design Automation Conference
Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic
IEEE Transactions on Computers
A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique
Journal of Electronic Testing: Theory and Applications
Design of asynchronous circuits for high soft error tolerance in deep submicrometer CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Soft-error tolerance and mitigation in asynchronous burst-mode circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Designing robust threshold gates against soft errors
Microelectronics Journal
VLSI implementation of a distributed algorithm for fault-tolerant clock generation
Journal of Electrical and Computer Engineering - Special issue on Clock/Frequency Generation Circuits and Systems
An infrastructure for accurate characterization of single-event transients in digital circuits
Microprocessors & Microsystems
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This paper addresses the issue of Single-Event Upset (SEU) in quasi delay-insensitive (QDI) asynchronous circuits. We show that an SEU can cause abnormal computations in QDI circuits beside deadlock, and we propose a generalmethod to make QDI circuits SEU-tolerant. We present a simplified SEU-tolerant buffer implementations for CMOS technology. Finally, we present a case study of a one-bit comparator and show SPICE-simulation results.