Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
The mutual exclusion problem: part I—a theory of interprocess communication
Journal of the ACM (JACM)
On the possibility and impossibility of achieving clock synchronization
Journal of Computer and System Sciences
Journal of the ACM (JACM)
Communications of the ACM
The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Integration, the VLSI Journal
Interconnected rings and oscillators as gigahertz clock distribution nets
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Practical Design of Globally-Asynchronous Locally-Synchronous Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Fourteen Ways to Fool Your Synchronizer
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
The Lutonium: A Sub-Nanojoule Asynchronous 8051 Microcontroller
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
On the Existence of Hazard-Free Multi-Level Logic
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Arbitration-free synchronization
Distributed Computing - Papers in celebration of the 20th anniversary of PODC
Analysis and verification of interconnected rings as clock distribution networks
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Fast and Low-Cost Clock Deskew Buffer
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Self-Timed Circuitry for Global Clocking
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Soft Errors in Advanced Computer Systems
IEEE Design & Test
Multiple Transient Faults in Logic: An Issue for Next Generation ICs
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
VLSI Implementation of a Fault-Tolerant Distributed Clock Generation
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
Fault-Tolerant Distributed Clock Generation in VLSI Systems-on-Chip
EDCC '06 Proceedings of the Sixth European Dependable Computing Conference
Impact of Variability on Clock Skew in H-tree Clock Networks
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
ASYNC '09 Proceedings of the 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (async 2009)
Improving Fault Tolerance by Using Reconfigurable Asynchronous Circuits
DDECS '08 Proceedings of the 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
A Metastability-Free Multi-synchronous Communication Scheme for SoCs
SSS '09 Proceedings of the 11th International Symposium on Stabilization, Safety, and Security of Distributed Systems
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
An infrastructure for accurate characterization of single-event transients in digital circuits
Microprocessors & Microsystems
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We present a novel approach for the on-chip generation of a fault-tolerant clock. Our method is based on the hardware implementation of a tick synchronization algorithm from the distributed systems community. We discuss the selection of an appropriate algorithm, present the refinement steps necessary to facilitate its efficient mapping to hardware, and elaborate on the key challenges we had to overcome in our actual ASIC implementation. Our measurement results confirm that the approach is indeed capable of creating a globally synchronized clock in a distributed fashion that is tolerant to a (configurable) number of arbitrary faults. This property facilitates eliminating the clock as a single point of failure. Our solution is based on purely asynchronous design, obviating the need for crystal oscillators. It is capable of adapting to parameter variations as well as changes in temperature and power supply-properties that are considered highly desirable for future technology nodes.