VLSI Implementation of a Fault-Tolerant Distributed Clock Generation

Authors:
M. Ferringer;G. Fuchs;A. Steininger;G. Kempf
Affiliations:
TU Vienna, Austria;TU Vienna, Austria;TU Vienna, Austria;Austrian Aerospace GmbH, Austria
Venue:
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
Year:
2006

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Abstract

This paper presents simulations of 3 different implementations of the minority-3 function, with special focus on mismatch analysis through statistical Monte Carlo-simulations. The simulations clearly favors the minority-3 Mirrored gate, and a gate-level ...