A Metastability-Free Multi-synchronous Communication Scheme for SoCs

Authors:
Thomas Polzer;Thomas Handl;Andreas Steininger
Affiliations:
Institute of Computer Engineering --- Embedded Computing Systems Group, Vienna University of Technology, Vienna, Austria A-1040;Institute of Computer Engineering --- Embedded Computing Systems Group, Vienna University of Technology, Vienna, Austria A-1040;Institute of Computer Engineering --- Embedded Computing Systems Group, Vienna University of Technology, Vienna, Austria A-1040
Venue:
SSS '09 Proceedings of the 11th International Symposium on Stabilization, Safety, and Security of Distributed Systems
Year:
2009

Citing 12
Cited 4

Interconnected rings and oscillators as gigahertz clock distribution nets

Proceedings of the 13th ACM Great Lakes symposium on VLSI
Timing Measurements of Synchronization Circuits

ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)

Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Trends and Challenges in VLSI Circuit Reliability

IEEE Micro
Arbitration-free synchronization

Distributed Computing - Papers in celebration of the 20th anniversary of PODC
Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing

IEEE Transactions on Computers
Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation

IEEE Micro
VLSI Implementation of a Fault-Tolerant Distributed Clock Generation

DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
Fault-Tolerant Distributed Clock Generation in VLSI Systems-on-Chip

EDCC '06 Proceedings of the Sixth European Dependable Computing Conference
Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures

NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A Survey and Taxonomy of GALS Design Styles

IEEE Design & Test
Metastable Behavior in Digital Systems

IEEE Design & Test

Fault-tolerant algorithms for tick-generation in asynchronous logic: robust pulse generation

SSS'11 Proceedings of the 13th international conference on Stabilization, safety, and security of distributed systems
VLSI implementation of a distributed algorithm for fault-tolerant clock generation

Journal of Electrical and Computer Engineering - Special issue on Clock/Frequency Generation Circuits and Systems
HEX: scaling honeycombs is easier than scaling clock trees

Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures
Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip

Journal of Computer and System Sciences

Quantified Score

Hi-index	0.00

Visualization

Abstract

We propose a communication scheme for GALS systems with independent but approximately synchronized clock sources, which guarantees high-speed metastability-free communication between any two peers via bounded-size FIFO buffers. The proposed approach can be used atop of any multi-synchronous clocking system that guarantees a synchronization precision in the order of several clock cycles, like our fault-tolerant DARTS clocks. We determine detailed formulas for the required communication buffer size, and prove that this choice indeed guarantees metastability-free communication between correct peers, at maximum clock speed. We also describe a fast and efficient implementation of our scheme, and calculate the required buffer size for a sample test scenario. Experimental results confirm that the size lower bounds provided by our formulas are tight in this setting.