Self-stabilizing systems in spite of distributed control
Communications of the ACM
Interconnected rings and oscillators as gigahertz clock distribution nets
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Timing Measurements of Synchronization Circuits
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
A Multi-PLL Clock Distribution Architecture for Gigascale Integration
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
IEEE Transactions on Computers
Self-Timed Circuitry for Global Clocking
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Clock Distribution Architectures: A Comparative Study
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Analyzing timing uncertainty in mesh-based clock architectures
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
A Metastability-Free Multi-synchronous Communication Scheme for SoCs
SSS '09 Proceedings of the 11th International Symposium on Stabilization, Safety, and Security of Distributed Systems
ISPD 2010 high performance clock network synthesis contest: benchmark suite and results
Proceedings of the 19th international symposium on Physical design
Routing with constraints for post-grid clock distribution in microprocessors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining
EDCC '10 Proceedings of the 2010 European Dependable Computing Conference
Fault-tolerant algorithms for tick-generation in asynchronous logic: robust pulse generation
SSS'11 Proceedings of the 13th international conference on Stabilization, safety, and security of distributed systems
Multilevel tree fusion for robust clock networks
Proceedings of the International Conference on Computer-Aided Design
Low-power clock trees for CPUs
Proceedings of the International Conference on Computer-Aided Design
Synchronization in digital system design
IEEE Journal on Selected Areas in Communications
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We argue that grid structures are a very promising alternative to the standard approach for distributing a clock signal throughout VLSI circuits and other hardware devices. Traditionally, this is accomplished by a delay-balanced clock tree, which distributes the signal supplied by a single clock source via carefully engineered and buffered signal paths. Our approach, termed HEX, is based on a hexagonal grid with simple intermediate nodes, which both control the forwarding of clock ticks in the grid and supply them to nearby functional units. HEX is Byzantine fault-tolerant, in a way that scales with the grid size, self-stabilizing, and seamlessly integrates with multiple synchronized clock sources, as used in multi-synchronous Globally Synchronous Locally Asynchronous (GALS) architectures. Moreover, HEX guarantees a small clock skew between neighbors even for wire delays that are only moderately balanced. We provide both a theoretical analysis of the worst-case skew and simulation results that demonstrate very small typical skew in realistic runs.