The design and implementation of a low-latency on-chip network
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
VLSI implementation of a distributed algorithm for fault-tolerant clock generation
Journal of Electrical and Computer Engineering - Special issue on Clock/Frequency Generation Circuits and Systems
HEX: scaling honeycombs is easier than scaling clock trees
Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures
Journal of Computer and System Sciences
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We present an apparatus used to distribute a timing reference or clock across the extent of a digital system. Self-timed circuitry both generates and distributes a clock signal, while using less power and less skew compared to a clock tree. HSpice simulations in a 180nm CMOS process comparing the Distributed Clock Generator presented in this paper and an H-tree clock distribution system, each clocking a 16mm 脳 16mm area suggests a 30% power savings. Also worst case skew was reduced from 27ps to 2ps while using a clock period equivalent to 9 FO4 gates.