Journal of the ACM (JACM)
Reaching Agreement in the Presence of Faults
Journal of the ACM (JACM)
Timing Measurements of Synchronization Circuits
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
IEEE Transactions on Computers
Self-stabilizing clock synchronization in the presence of Byzantine faults
Journal of the ACM (JACM)
Fault-Tolerant Distributed Clock Generation in VLSI Systems-on-Chip
EDCC '06 Proceedings of the Sixth European Dependable Computing Conference
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
Fast self-stabilizing byzantine tolerant digital clock synchronization
Proceedings of the twenty-seventh ACM symposium on Principles of distributed computing
On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation Scheme
ASYNC '09 Proceedings of the 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (async 2009)
A Metastability-Free Multi-synchronous Communication Scheme for SoCs
SSS '09 Proceedings of the 11th International Symposium on Stabilization, Safety, and Security of Distributed Systems
Self-stabilizing Byzantine digital clock synchronization
SSS'06 Proceedings of the 8th international conference on Stabilization, safety, and security of distributed systems
A Byzantine-fault tolerant self-stabilizing protocol for distributed clock synchronization systems
SSS'06 Proceedings of the 8th international conference on Stabilization, safety, and security of distributed systems
Self-stabilizing pulse synchronization inspired by biological pacemaker networks
SSS'03 Proceedings of the 6th international conference on Self-stabilizing systems
Low-overhead error detection for networks-on-chip
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining
EDCC '10 Proceedings of the 2010 European Dependable Computing Conference
General theory of metastable operation
IEEE Transactions on Computers
HEX: scaling honeycombs is easier than scaling clock trees
Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures
An infrastructure for accurate characterization of single-event transients in digital circuits
Microprocessors & Microsystems
Journal of Computer and System Sciences
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The advances of deep submicron VLSI technology pose new challenges in designing robust systems, which can in principle be addressed by approaches established in fault-tolerant distributed systems research. This paper is the first step in an attempt to develop a very robust high-precision clocking system for hardware designs like systemson-chip for critical applications. It is devoted to the design and the correctness proof of a novel Byzantine fault-tolerant self-stabilizing pulse synchronization protocol, which facilitates a direct implementation in standard asynchronous digital logic. Despite the severe implementation constraints, it offers optimal resilience and smaller complexity than all existing pulse synchronization protocols.