A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Analysis of Error Recovery Schemes for Networks on Chips
IEEE Design & Test
Worst-case Traffic for Oblivious Routing Functions
IEEE Computer Architecture Letters
Exploring Fault-Tolerant Network-on-Chip Architectures
DSN '06 Proceedings of the International Conference on Dependable Systems and Networks
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Selective shielding: a crosstalk-free bus encoding technique
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Interconnect-Centric Design for Advanced SOC and NOC
Interconnect-Centric Design for Advanced SOC and NOC
Fault-tolerant algorithms for tick-generation in asynchronous logic: robust pulse generation
SSS'11 Proceedings of the 13th international conference on Stabilization, safety, and security of distributed systems
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In the current deep sub-micron age, interconnect reliability is a subject of major concern, and is crucial for a successful product. Coding is a widely-used method to achieve communication reliability, which can be very useful in a Network-on-Chip (NoC). A key challenge for NoC error detection is to provide a defined detection level, while minimizing the number of redundant parity bits, using small encoder and decoder circuits, and ensuring shortest path routing. We present Parity Routing (PaR), a novel method to reduce the number of redundant bits transmitted. PaR exploits NoC path diversity to reduce the number of redundant parity bits. Our analysis shows that, for example, on a 4×4 NoC with a demand of one parity bit, PaR reduces the redundant information transmitted by 75%, and the savings increase asymptotically to 100% with the size of the NoC. In addition, we show that PaR can yield power savings due to the reduced number of bit transmissions and simple decoding process. Furthermore, PaR utilizes low complexity, small-area circuits.