Analysis of Error Recovery Schemes for Networks on Chips

Authors:
Srinivasan Murali;Theocharis Theocharides;N. Vijaykrishnan;Mary Jane Irwin;Luca Benini;Giovanni De Micheli
Affiliations:
Stanford University;Pennsylvania State University;Pennsylvania State University;Pennsylvania State University;University of Bologna;Ecole Polytechnique Federale de Lausanne
Venue:
IEEE Design & Test
Year:
2005

Citing 14
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Abstract

Error resiliency is a must for NoCs, but it must not incur undue costs--particularly in terms of energy consumption. Here, the authors present anauthoritative discussion of the trade-offs involved in various error recoveryschemes, enabling designers to make optimal decisions.