Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
Reducing bus delay in submicron technology using coding
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Active shields: a new approach to shielding global wires
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Formulae and applications of interconnect estimation considering shield insertion and net ordering
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Optimal shielding/spacing metrics for low power design
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Buffer insertion for noise and delay optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis of Error Recovery Schemes for Networks on Chips
IEEE Design & Test
Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Delay and peak power minimization for on-chip buses using temporal redundancy
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A bus architecture for crosstalk elimination in high performance processor design
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Exploiting on-chip data behavior for delay minimization
Proceedings of the 2007 international workshop on System level interconnect prediction
Information theoretic approach to address delay and reliability in long on-chip interconnects
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Bus encoding schemes for minimizing delay in VLSI interconnects
Proceedings of the 20th annual conference on Integrated circuits and systems design
Parallel vs. serial on-chip communication
Proceedings of the 2008 international workshop on System level interconnect prediction
Bus encoding for simultaneous delay and energy optimization
Proceedings of the 13th international symposium on Low power electronics and design
Data handling limits of on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Selective shielding technique to eliminate crosstalk transitions
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Delay-efficient bus encoding techniques
Microprocessors & Microsystems
NCXplore: a design space exploration framework of temporal encoding for on-chip serial interconnects
International Journal of High Performance Systems Architecture
Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect
Microelectronics Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Crosstalk between wires, caused by increased capacitive coupling, is considered one of the major factors that affect the performance of interconnects such as buses. The data-dependent nature of crosstalk-induced delays necessitates bus cycle time to be designed for the worst case crosstalk. However, this pessimism incurs a significant performance penalty. Consequently, we propose a crosstalk aware inter-connect that uses a faster clock and dynamically controls the number of cycles required for transmission based onthe estimated delay of the data pattern to be transmitted. In order to accomplish this, we designed a crosstalk analyzer circuit that is incorporated into the sender side of the bus and support a variable cycle transmission mechanism. We evaluate the effectiveness of the proposed scheme focusing on the on-chip buses of a microprocessor and by using the SPEC2000 benchmarks. The experimental results show that the proposed approach improves performance by 31.5% as compared to the original pessimistic approach. Furthermore, we employ a coding optimization to enhance the effectiveness of the proposed approach. We also show that the proposed scheme is an area-efficient approach to improving performance as compared to other crosstalk reduction schemes.