Minimum crosstalk switchbox routing
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Buffer insertion for noise and delay optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Figures of merit to characterize the importance of on-chip inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
A novel VLSI layout fabric for deep sub-micron applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
IC analyses including extracted inductance models
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Simultaneous signal and power routing under K model
Proceedings of the 2001 international workshop on System-level interconnect prediction
Simultaneous shield insertion and net ordering under explicit RLC noise constraint
Proceedings of the 38th annual Design Automation Conference
Fitting Equations to Data: Computer Analysis of Multifactor Data
Fitting Equations to Data: Computer Analysis of Multifactor Data
Effects of global interconnect optimizations on performance estimation of deep submicron design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post global routing crosstalk synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Shield count minimization in congested regions
Proceedings of the 2002 international symposium on Physical design
Towards global routing with RLC crosstalk constraints
Proceedings of the 39th annual Design Automation Conference
Routing methodology for minimizing 1nterconnect energy dissipation
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Reduction of coupling effects by optimizing the 3-D configuration of the routing grid
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
A Crosstalk Aware Interconnect with Variable Cycle Transmission
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Reduction of crosstalk noise by optimizing 3-D configuration of the routing grid
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Shielding area optimization under the solution of interconnect crosstalk
Journal of Computer Science and Technology
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Exploiting on-chip data behavior for delay minimization
Proceedings of the 2007 international workshop on System level interconnect prediction
On optimal ordering of signals in parallel wire bundles
Integration, the VLSI Journal
Selective shielding: a crosstalk-free bus encoding technique
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Forbidden transition free crosstalk avoidance CODEC design
Proceedings of the 45th annual Design Automation Conference
A bit-stuffing algorithm for crosstalk avoidance in high speed switching
INFOCOM'10 Proceedings of the 29th conference on Information communications
Efficient on-chip crosstalk avoidance CODEC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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It has been shown recently that simultaneous shield insertion and net ordering (called SINO/R as only random shields are used) provides an area-efficient solution to reduce the RLC noise. In this paper, we first develop simple formulae with errors less than 10% to estimate the number of shields in the min-area SINO/R solution. In order to accommodate pre-routed P/G wires that also serve as shields, we then formulate two new SINO problems: SINO/SPR and SINO/UPG, and propose effective and efficient two-phase algorithms to solve them. Compared to the existing dense wiring fabric scheme, the resulting SINO/SPR and SINO/UPG schemes maintain the regularity of the P/G structure, have negligible penalty on noise and delay variation, and reduce the total routing area by up to 42% and 36%, respectively. Further, we develop various pre-layout estimation formulae for shielding areas and optimal P/G structures under different routing styles. These formulae can be readily used to guide global routing and high-level design decisions.