Techniques for crosstalk avoidance in the physical design of high-performance digital systems
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Minimum crosstalk switchbox routing
Integration, the VLSI Journal
Global routing with crosstalk constraints
DAC '98 Proceedings of the 35th annual Design Automation Conference
Timing and crosstalk driven area routing
DAC '98 Proceedings of the 35th annual Design Automation Conference
A novel VLSI layout fabric for deep sub-micron applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Optimal reliable crosstalk-driven interconnect optimization
ISPD '00 Proceedings of the 2000 international symposium on Physical design
On the relevance of wire load models
Proceedings of the 2001 international workshop on System-level interconnect prediction
Formulae and applications of interconnect estimation considering shield insertion and net ordering
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A postprocessing algorithm for crosstalk-driven wire perturbation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis and Optimization of Power Grids
IEEE Design & Test
Simultaneous shield and buffer insertion for crosstalk noise reduction in global routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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With worsening crosstalk in nanometer designs, it is becoming increasingly important to control the switching cross-coupling experienced by critical wires. This is commonly done by adding shields adjacent to these wires. However, the number of wires requiring shields in high frequency designs becomes extremely large, resulting in a large area impact. We address this problem at both the methodological and algorithmic levels in this paper, integrating the traditionally separate steps of power and signal routing in a safe manner to minimize the number of shields required to satisfy all shielding constraints. We postpone the power routing in middle metal layers to after critical signal nets and their shields have been laid out (with maximal shield sharing), and then try to construct a fine-grained power grid out of the already routed shields. Given a routing on a metal layer, our adaptive power routing algorithm adds provably fewest new power lines to complete the power grid on that layer. Our approach has proven highly effective while designing some high frequency blocks of a commercial gigahertz range microprocessor.