Minimum crosstalk channel routing
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A spacing algorithm for performance enhancement and cross-talk reduction
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Post global routing crosstalk risk estimation and reduction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An optimal algorithm for river routing with crosstalk constraints
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Digital sensitivity: predicting signal interaction using functional analysis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A practical clock router that accounts for the capacitance derived from parallel and cross segments
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Analysis, reduction and avoidance of crosstalk on VLSI chips
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Global routing with crosstalk constraints
DAC '98 Proceedings of the 35th annual Design Automation Conference
Optimal river routing with crosstalk constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The deep sub-micron signal integrity challenge
ISPD '99 Proceedings of the 1999 international symposium on Physical design
A novel VLSI layout fabric for deep sub-micron applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Pseudo pin assignment with crosstalk noise control
ISPD '00 Proceedings of the 2000 international symposium on Physical design
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Domino logic synthesis minimizing crosstalk
Proceedings of the 37th Annual Design Automation Conference
Shield count minimization in congested regions
Proceedings of the 2002 international symposium on Physical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Behavioral Transformations to Increase Noise Immunity in Asynchronous Specifications
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Driver modeling and alignment for worst-case delay noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Coupling aware timing optimization and antenna avoidance in layer assignment
Proceedings of the 2005 international symposium on Physical design
Formal derivation of optimal active shielding for low-power on-chip buses
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A perturbation-aware noise convergence methodology for high frequency microprocessors
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Wire density driven global routing for CMP variation and timing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
On optimal ordering of signals in parallel wire bundles
Integration, the VLSI Journal
CT-RSA '09 Proceedings of the The Cryptographers' Track at the RSA Conference 2009 on Topics in Cryptology
Extended global routing with RLC crosstalk constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Crosstalk noise reduction in synthesized digital logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On pioneering nanometer-era routing problems
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
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Interconnect performance does not scale well into deep submicron dimensions, and the rising number of analog effects erodes the digital abstraction necessary for high levels of integration. In particular, crosstalk is an analog phenomenon of increasing relevance. To cope with the increasingly analog nature of high-performance digital system design, we propose using a constraint-driven methodology. In this paper we describe new constraint generation ideas incorporating digital sensitivity. In constraint-driven synthesis, we show that a fundamental subproblem of crosstalk channel routing, coupling-constrained graph levelization (CCL), is NP-complete, and develop a novel heuristic algorithm. To demonstrate the viability of our methodology, we introduce a gridless crosstalk-avoiding channel router as an example of a robust and truly constraint-driven synthesis tool.