Post global routing crosstalk risk estimation and reduction

Authors:
Tianxiong Xue;Ernest S. Kuh;Dongsheng Wang
Affiliations:
Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA;Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA;Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA
Venue:
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Year:
1997

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Abstract

Previous approaches for crosstalk synthesis often fail to achieve satisfactory results due to limited routing flexibility. Furthermore, the risk tolerance bounds partitioning problem critical for constrained optimization has not been adequately addressed. This paper presents the first approach for crosstalk risk estimation and reduction at the global (instead of detailed) routing level. It quantitatively defines and estimates the risk of each routing region using a graph-based optimization approach and globally adjusts routes of nets for risk reduction. At the end of the entire optimization process, a risk-free global routing solution is obtained together with partitions of nets' risk tolerance bounds which reflect the crosstalk situation of the chip. The proposed approach has been implemented and tested on CBL/NCSU benchmarks and the experimental results are very promising.