An efficient multilayer MCM router based on four-via routing
DAC '93 Proceedings of the 30th international Design Automation Conference
Algorithmic aspects of three dimensional MCM routing
DAC '94 Proceedings of the 31st annual Design Automation Conference
Post global routing crosstalk risk estimation and reduction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
SURF: Rubber-Band Routing System for Multichip Modules
IEEE Design & Test
Performance-Driven Interconnect Global Routing
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
An MCM/IC Timing-Driven Placement Algorithm Featuring Explicit Design Space Exploration
MCMC '96 Proceedings of the 1996 IEEE Multi-Chip Module Conference (MCMC '96)
Performance driven multi-layer general area routing for PCB/MCM designs
DAC '98 Proceedings of the 35th annual Design Automation Conference
A performance-driven MCM router with special consideration of crosstalk reduction
Proceedings of the conference on Design, automation and test in Europe
Multilevel approach to full-chip gridless routing
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A novel framework for multilevel routing considering routability and performance
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An enhanced multilevel routing system
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Multilevel full-chip gridless routing considering optical proximity correction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
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In high-performance multilayer routing, time delay is an important performance issue which has not been appropriately addressed by previous multilayer routing approaches. This paper proposes a new timing-driven MCM/IC multilayer routing algorithm, named MLR, considering the Elmore delay as well as some other fundamental performance issues, such as the number of layers, vias and the total wirelength. Algorithm MLR assigns all the nets into the routing layers layer-pair by layer-pair based on the layer assignment algorithm. During each pair-layer routing, the timing-driven Steiner area routing algorithm SOAR is used to generate a Steiner tree for each net while minimizing the Elmore delay of the net. For two nodes to be connected for the net being routed, an optimal path from one node to the other is created by the (/spl alpha/,/spl beta/)* algorithm. Additionally, when power and ground nets are considered, some signal nets are routed in the limited routing space on the power and ground layer-pair, which is very useful in decreasing the number of layers needed to complete the routing. The proposed algorithm has been implemented and tested on CBL/NCSU and MCC benchmarks and the experimental results are very promising.