Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Performance driven multi-layer general area routing for PCB/MCM designs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Timing and crosstalk driven area routing
DAC '98 Proceedings of the 35th annual Design Automation Conference
Multilevel hypergraph partitioning: applications in VLSI domain
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interconnect estimation and planning for deep submicron designs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
DUNE: a multi-layer gridless routing system with wire planning
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Provably good global routing by a new approximation algorithm for multicommodity flow
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Performance driven multi-level and multiway partitioning with retiming
Proceedings of the 37th Annual Design Automation Conference
Routing tree construction under fixed buffer locations
Proceedings of the 37th Annual Design Automation Conference
An implicit connection graph maze routing algorithm for ECO routing
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Multilevel optimization for large-scale circuit placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Faster and Simpler Algorithms for Multicommodity Flow and other Fractional Packing Problems.
FOCS '98 Proceedings of the 39th Annual Symposium on Foundations of Computer Science
DAC '78 Proceedings of the 15th Design Automation Conference
A solution to line-routing problems on the continuous plane
DAC '69 Proceedings of the 6th annual Design Automation Conference
A New Timing-Driven Multilayer MCM/IC Routing Algorithm
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
A global router with a theoretical bound on the optimal solution
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pseudopin assignment with crosstalk noise control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A novel framework for multilevel routing considering routability and performance
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An enhanced multilevel routing system
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Multilevel floorplanning/placement for large-scale modules using B*-trees
Proceedings of the 40th annual Design Automation Conference
Full-Chip Multilevel Routing for Power and Signal Integrity
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Multilevel routing with antenna avoidance
Proceedings of the 2004 international symposium on Physical design
A Fast Crosstalk- and Performance-Driven Multilevel Routing System
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multilevel full-chip routing with testability and yield enhancement
Proceedings of the 2005 international workshop on System level interconnect prediction
Improved multilevel routing with redundant via placement for yield and reliability
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Multilevel full-chip routing for the X-based architecture
Proceedings of the 42nd annual Design Automation Conference
A novel framework for multilevel full-chip gridless routing
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Thermal-driven multilevel routing for 3-D ICs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Multilevel full-chip gridless routing considering optical proximity correction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Probabilistic congestion model considering shielding for crosstalk reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 2006 international symposium on Physical design
IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Novel full-chip gridless routing considering double-via insertion
Proceedings of the 43rd annual Design Automation Conference
Full-chip multilevel routing for power and signal integrity
Integration, the VLSI Journal
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
PIXAR: A performance-driven X-architecture router based on a novel multilevel framework
Integration, the VLSI Journal
Rover: routing on via-configurable fabrics for standard-cell-like structured ASICs
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Efficient congestion mitigation using congestion-aware steiner trees and network coding topologies
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
BonnRoute: Algorithms and data structures for fast and good VLSI routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper presents a novel gridless detailed routing approach based on multilevel optimization. The multilevel framework with recursive coarsening and refinement in a "V-shaped" flow allows efficient scaling of our gridless detailed router to very large designs. The downward pass of recursive coarsening builds the representations of routing regions at different levels, while the upward pass of iterative refinement allows a gradual convergence to a globally optimized solution. The use of a multicommodity flow-based routing algorithm for the initial routing at the coarsest level and a modified maze algorithm for the refinement at each level considerably improves the quality of gridless routing results. Compared with the recently published gridless detailed routing algorithm using wire planning [1], our multilevel gridless routing algorithm is 3× to 75× faster. We also compared our multilevel framework with a recently developed three-level routing approach [1] and a traditional hierarchical routing approach. Our multilevel algorithm generates better detailed routing results with higher completion rates. To our knowledge, this is the first time that multilevel optimization has been applied to IC routing.