Data structures and network algorithms
Data structures and network algorithms
A spacing algorithm for performance enhancement and cross-talk reduction
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Global routing with crosstalk constraints
DAC '98 Proceedings of the 35th annual Design Automation Conference
Multilevel hypergraph partitioning: applications in VLSI domain
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DUNE: a multi-layer gridless routing system with wire planning
ISPD '00 Proceedings of the 2000 international symposium on Physical design
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Timing-driven routing for symmetrical array-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Introduction to Algorithms
Multilevel optimization for large-scale circuit placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Multilevel approach to full-chip gridless routing
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A novel framework for multilevel routing considering routability and performance
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An enhanced multilevel routing system
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Track assignment: a desirable intermediate step between global routing and detailed routing
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Multilevel floorplanning/placement for large-scale modules using B*-trees
Proceedings of the 40th annual Design Automation Conference
A solution to line-routing problems on the continuous plane
DAC '69 Proceedings of the 6th annual Design Automation Conference
On the complexity of bicriteria spanning tree problems for a set of points in the plane
On the complexity of bicriteria spanning tree problems for a set of points in the plane
Multilevel circuit partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Global routing by new approximation algorithms for multicommodity flow
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pattern routing: use and theory for increasing predictability and avoiding coupling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilevel routing with antenna avoidance
Proceedings of the 2004 international symposium on Physical design
Coupling aware timing optimization and antenna avoidance in layer assignment
Proceedings of the 2005 international symposium on Physical design
Improved multilevel routing with redundant via placement for yield and reliability
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Moment-driven coupling-aware routing methodology
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Multilevel full-chip routing for the X-based architecture
Proceedings of the 42nd annual Design Automation Conference
A novel framework for multilevel full-chip gridless routing
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Timing driven track routing considering coupling capacitance
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Multilevel full-chip gridless routing considering optical proximity correction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 2006 international symposium on Physical design
IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Crosstalk-aware domino logic synthesis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Multilevel routing with jumper insertion for antenna avoidance
Integration, the VLSI Journal
Optimizing yield in global routing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Wire density driven global routing for CMP variation and timing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2008 international symposium on Physical design
A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
PIXAR: A performance-driven X-architecture router based on a novel multilevel framework
Integration, the VLSI Journal
Extended global routing with RLC crosstalk constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we propose a novel framework for fast multilevelrouting considering crosstalk and performance optimization. To handlethe crosstalk minimization problem, we incorporate an intermediatestage of layer/track assignment into the multilevel routing framework.For performance-driven routing, we propose a novel minimum-radiusminimum-cost spanning-tree (MRMCST) heuristic for global routing.Compared with the state-of-the-art multilevel routing, the experimentalresults show that our approach achieved a 6.7X runtime speedup, reducedthe respective maximum and average crosstalk (coupling length)by about 30% and 24%, reduced the respective maximum and averagedelay by about 15% and 5%, and resulted in fewer failed nets.