The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Crosstalk constrained global route embedding
ISPD '99 Proceedings of the 1999 international symposium on Physical design
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Towards global routing with RLC crosstalk constraints
Proceedings of the 39th annual Design Automation Conference
Track assignment: a desirable intermediate step between global routing and detailed routing
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A Fast Crosstalk- and Performance-Driven Multilevel Routing System
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Minimum crosstalk channel routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
TIGER: an efficient timing-driven global router for gate array and standard cell layout design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post global routing crosstalk synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Global routing with crosstalk constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing- and crosstalk-driven area routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pseudopin assignment with crosstalk noise control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect sizing and spacing with consideration of coupling capacitance
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A timing-constrained simultaneous global routing algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On integrating power and signal routing for shield count minimization in congested regions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Coupling aware timing optimization and antenna avoidance in layer assignment
Proceedings of the 2005 international symposium on Physical design
Wire density driven global routing for CMP variation and timing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
TROY: track router with yield-driven wire planning
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 2008 international symposium on Physical design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Track routing optimizing timing and yield
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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As VLSI technology enters the ultra-deep submicron era, wire coupling capacitance starts to dominate self capacitance and can no longer be neglected in timing driven routing. In this paper, a coupling aware timing driven track routing heuristic is proposed. Given a global routing solution and timing constraint for each net, major trunks of wire segments are assigned to routing tracks such that the minimum timing slack among all nets is maximized. Delay penalties from both coupling capacitance and wire detour are considered in a unified graph model. The core problem is formulated and solved as a Sequential Ordering Problem (SOP). Routing blockages are handled in a post processing procedure. The experimental results on benchmark circuits show that the effect of coupling capacitance on timing is significant and the proposed heuristic results in greater improvement on coupling aware timing compared with other approaches.