Analysis, reduction and avoidance of crosstalk on VLSI chips
ISPD '98 Proceedings of the 1998 international symposium on Physical design
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Crosstalk minimization using wire perturbations
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Reducing cross-coupling among interconnect wires in deep-submicron datapath design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Pseudo pin assignment with crosstalk noise control
ISPD '00 Proceedings of the 2000 international symposium on Physical design
A crosstalk-aware timing-driven router for FPGAs
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Self-reforming routing for stochastic search in VLSI interconnection layout
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Crosstalk noise estimation for noise management
Proceedings of the 39th annual Design Automation Conference
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Layer assignment for crosstalk risk minimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Coupling aware timing optimization and antenna avoidance in layer assignment
Proceedings of the 2005 international symposium on Physical design
Timing driven track routing considering coupling capacitance
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Priority-based routing resource assignment considering crosstalk
Journal of Computer Science and Technology
Power-delay optimization in VLSI microprocessors by wire spacing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient shield insertion for inductive noise reduction in nanometer technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast waveform estimation (FWE) for timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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As technology advances, interconnection wires are placed in closer proximity and circuits operate at higher frequencies. Consequently, reduction of crosstalk between interconnection wires becomes an important consideration in VLSI design. In this paper, we study the gridded channel routing problem with the objective of satisfying crosstalk constraints for the nets. We proposed a new approach to the problem which utilizes existing channel routing algorithms and improves upon the routing results by permuting the routing tracks. The permutation problem is proven to be NP-complete. A novel mixed ILP formulation and effective procedures for reducing the number of variables and constraints in the mixed ILP formulation are then presented. The new algorithm is tested on three large benchmark circuits as well as many randomly generated circuits. The experimental results are very promising