Placement and routing tools for the Triptych FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An optimal algorithm for river routing with crosstalk constraints
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
A performance-driven MCM router with special consideration of crosstalk reduction
Proceedings of the conference on Design, automation and test in Europe
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
A New Switch Block for Segmented FPGAs
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Deep Sub-Micron Static Timing Analysis in Presence of Crosstalk
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Efficient Delay Calculation in Presence of Crosstalk
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Crosstalk Aware Static Timing Analysis: A Two Step Approach
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
COP: a Crosstalk OPtimizer for gridded channel routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimum crosstalk channel routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A postprocessing algorithm for crosstalk-driven wire perturbation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 40th annual Design Automation Conference
Solving hard instances of FPGA routing with a congestion-optimal restrained-norm path search space
Proceedings of the 2007 international symposium on Physical design
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Optimizing effective interconnect capacitance for FPGA power reduction
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk is an important physical phenomenon that must be taken into account. Crosstalk has primarily been a concern for ASICs, multi-chip modules, and custom chips, however, it will soon become a concern in FPGAs. In this paper, we describe the first published crosstalk-aware router that targets FPGAs. We show that, in a representative FPGA architecture implemented in a 0.18mm technology, the average routing delay in the presence of crosstalk can be reduced by 7.1% compared to a router with no knowledge of crosstalk. About half of this improvement is due to a tighter delay estimator, and half is due to an improved routing algorithm.