PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
FPGA routing and routability estimation via Boolean satisfiability
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Architectural and physical design challenges for one-million gate FPGAs and beyond
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Proceedings of the 1997 international symposium on Physical design
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
New parallelization and convergence results for NC: a negotiation-based FPGA router
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
A crosstalk-aware timing-driven router for FPGAs
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Proceedings of the 2001 international symposium on Physical design
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
A router for symmetrical FPGAs based on exact routing density evaluation
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Wire type assignment for FPGA routing
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
PipeRoute: a pipelining-aware router for FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A Min-Cost Flow Based Detailed Router for FPGAs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Simultaneous short-path and long-path timing optimization for FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Timing-driven routing for FPGAs based on Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-performance routing at the nanometer scale
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Improving FPGA routability using network coding
Proceedings of the 18th ACM Great Lakes symposium on VLSI
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The negotiated congestion mechanism forms the basis of most published FPGA routers today, with many routers projecting congestion and any other requirements onto a scalar search space to evaluate candidate paths. In this paper, we study the numerical stability of these scalar projections as the number of iterations increase. We show that in these scalar search spaces the norm of path costs increase exponentially with the number of iterations, leading to floating-point absorption and representation problems in computer arithmetic. We propose a novel two-component totally-ordered monoid space for path candidate evaluation, that guarantees the A* search finds a path with minimum congestion cost, and has linear norm growth with respect to the number of iterations. We demonstrate the efficacy of our new algorithm by testing on hard open routing problems in the FPGA Place and Route Challenge. The router successfully found 18 new routing solutions to instances that were previously unroutable, reducing the lowest track count to route 20 standard FPGA routing benchmarks by 10.2%.