A global router using an efficient approximate multicommodity multiterminal flow algorithm
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
Finding minimum-cost flows by double scaling
Mathematical Programming: Series A and B
An efficient timing-driven global routing algorithm
DAC '93 Proceedings of the 30th international Design Automation Conference
PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
A performance and routablity driven router for FPGAs considering path delays
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
New performance-driven FPGA routing algorithms
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Proceedings of the 1997 international symposium on Physical design
A fast routability-driven router for FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Provably good global routing by a new approximation algorithm for multicommodity flow
ISPD '00 Proceedings of the 2000 international symposium on Physical design
FPGA global routing based on a new congestion metric
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Timing-Driven Routing for Symmetrical-Array-Based FPGAs
ICCD '98 Proceedings of the International Conference on Computer Design
Solving hard instances of FPGA routing with a congestion-optimal restrained-norm path search space
Proceedings of the 2007 international symposium on Physical design
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
| Hi-index | 0.00 |
Routing for FPGAs has been a very challenging problem dueto the limitation of routing resources. Although the FPGArouting problem has been researched extensively, most algorithms route one net at a time, and it can cause the net-ordering problem.In this paper, we present a detailed routing algorithm forFPGAs based on min-cost flow computations. Using themin-cost flow approach, our algorithm routes all the netsconnected to a common logic module simultaneously. Ateach stage of the network flow computation, we guaranteeoptimal result in terms of routability and delay cost. For further improvement, we adopt an iterative re nement scheme based on the Lagrangian relaxation technique. The Lagrangian relaxation approach transforms the routing problem into a sequence of Lagrangian subproblems. At each iteration of the algorithm, Lagrangian subproblems are solvedby our min-cost flow based routing algorithm. Any violationof congestion constraints is reflected in the value of corresponding Lagrangian multiplier. The Lagrangian multipliers are incorporated into the cost of each routing rosource nodeand guide the router.Because our min-cost flow based algorithm minimizes costfunction while it maximizes the flow, our algorithm findscongestion-free routing solutions with minimum total delay.Comparison with VPR router shows that our router usesless or equal number of routing tracks with smaller criticalpath delay as well as total routing delay.