Timing-driven routing for FPGAs based on Lagrangian relaxation
Proceedings of the 2002 international symposium on Physical design
A timing-constrained algorithm for simultaneous global routing of multiple nets
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Wire type assignment for FPGA routing
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
A Min-Cost Flow Based Detailed Router for FPGAs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Timing-constrained congestion-driven global routing
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
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In this paper, we present a timing-driven global router for symmetrical-array-based FPGAs. The routing resources in the symmetrical-array-based FPGAs consist of segments of various lengths. Researchers have shown that the number of segments, instead of wirelength, used by a net is the most critical factor in controlling routing delay in an FPGA. Thus, traditional measure of routing delay based on the geometric distance of a signal is not accurate. To consider wirelength and delay simultaneously, we study a model of timing-driven routing trees, arising from the special properties of FPGA routing architectures. We explore the complexity of the routing-tree problem and present efficient and effective approximation algorithms for the problem. Based on the solutions to the routing-tree problem, we present a global-routing algorithm which is able to utilize various routing segments with global consideration to meet the timing constraints. Experimental results on benchmark circuits show that our approach is promising.