A timing-constrained algorithm for simultaneous global routing of multiple nets

Authors:
Jiang Hu;Sachin S. Sapatnekar
Affiliations:
University of Minnesota, Minneapolis, MN;University of Minnesota, Minneapolis, MN
Venue:
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Year:
2000

Citing 12
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Abstract

In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provides a general framework that may use any single-net routing algorithm and any delay model in global routing. It is based on the observation that there are several routing topology flexibilities under timing constraints. These flexibilities are exploited for congestion reduction through a network flow based hierarchical bisection and assignment process. Experimental results on benchmark circuits are quite promising.