A global router based on a multicommodity flow model
Integration, the VLSI Journal
PHIGURE: a parallel hierarchical global router
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Benchmarks for layout synthesis—evolution and current status
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A global router using an efficient approximate multicommodity multiterminal flow algorithm
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A new algorithm for standard cell global routing
Integration, the VLSI Journal
Iterative and adaptive slack allocation for performance-driven layout and FPGA routing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Performance-driven Steiner tree algorithm for global routing
DAC '93 Proceedings of the 30th international Design Automation Conference
An efficient timing-driven global routing algorithm
DAC '93 Proceedings of the 30th international Design Automation Conference
Performance-driven interconnect design based on distributed RC delay model
DAC '93 Proceedings of the 30th international Design Automation Conference
Simultaneous driver and wire sizing for performance and power optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
A global router optimizing timing and area for high-speed bipolar LSI's
DAC '94 Proceedings of the 31st annual Design Automation Conference
Timing driven placement for large standard cell circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Optimal wire sizing and buffer insertion for low power and a generalized delay model
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A sequential quadratic programming approach to concurrent gate and wire sizing
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Optimal wiresizing for interconnects with multiple sources
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Optimal wire-sizing formula under the Elmore delay model
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Buffered Steiner tree construction with wire sizing for interconnect layout optimization
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
A new feed-through assignment algorithm based on a flow model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
TimberWolf3.2: a new standard cell placement and global routing package
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Reducing channel density in standard cell layout
DAC '83 Proceedings of the 20th Design Automation Conference
Near-optimal critical sink routing tree constructions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal wiresizing under Elmore delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance driven multi-layer general area routing for PCB/MCM designs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Partitioning by iterative deletion
ISPD '99 Proceedings of the 1999 international symposium on Physical design
A novel technique for sea of gates global routing
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Preferred direction Steiner trees
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
A timing-constrained algorithm for simultaneous global routing of multiple nets
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A novel framework for multilevel routing considering routability and performance
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Gradual Relaxation Techniques with Applications to Behavioral Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Timing-constrained congestion-driven global routing
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Is probabilistic congestion estimation worthwhile?
Proceedings of the 2005 international workshop on System level interconnect prediction
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